1. The Field of the Invention
The present invention relates to systems and methods for obtaining digital representations of analog electrical signals. More specifically, the present invention relates to systems and methods for performing analog-to-digital conversion using transconveyance (charge-transfer) amplifiers.
2. Background and Relevant Art
There currently exists a strong demand for high-performance semiconductor circuits with reduced power dissipation. This demand is driven by a need for highly mobile and highly functional electronics in a variety of industries such as, for example, medicine, communications, military, and home. One particular type of circuit where this demand for reduced power dissipation exists is in analog-to-digital converters (xe2x80x9cADCsxe2x80x9d). ADCs can significantly influence the cost of interfacing to real world signals including, sound, motion, vibration, light intensity, or electrical, and in some cases ADCs can account for up to half of the total power consumed by an integrated circuit. Consequently, power dissipation reduction techniques for ADCs, particularly those techniques that preserve high performance in terms of accuracy, speed, and size, are highly desirable.
There are many circuits and methods conventionally available for performing analog-to-digital conversion. Typically, an analog electrical signal (or a mechanical signal such as a vibration or sound) is sampled, digital values are generated from the samples, and multiple digital values are combined to provide a meaningful digital representation of the analog electrical signal.
Some common types of ADCs include flash converters, subranging converters, pipeline converters, flash-flash converters, delta sigma modulators, and successive approximation converters. Such ADCs often include some number of amplifiers, typically voltage-to-current amplifiers (also frequently referred to as transconductance amplifiers) or voltage-to-voltage amplifiers. The overall performance of these ADCs relies heavily on the properties of these amplifiers, since input and reference voltages feed directly to these amplifiers.
FIG. 1 illustrates a flash ADC 100 that utilizes multiple amplifiers during the analog-to-digital conversion process. The operation of the flash ADC 100 will now be described in order to illustrate the basic principles of analog-to-digital conversion.
Each amplifier in preamplifiers 102 receives two input signals, the analog input 105 and a reference voltage (e.g., one of reference voltages 101). The reference voltages 101 vary incrementally. Preamplifiers 102 generate amplified output signals by amplifying the difference in the analog input and a corresponding reference voltage. Decision circuits 103 receive the amplified output signals and convert the amplified output signals to voltages representing a digital value of a logical xe2x80x9c1xe2x80x9d or xe2x80x9c0.xe2x80x9d Encoding logic 104 receives the representative digital values and maps the digital values into a meaningful digital representation of the analog input. As shown in FIG. 1, there is at least one amplifier for each digital value generated by flash analog-to-digital converter 100.
Flash ADCs are often desirable because conversion from an analog signal to a digital representation is performed in a single step, or a xe2x80x9cflash.xe2x80x9d However, the resolution (the number of digital output bits generated) of flash converters, such as flash ADC 100 is constrained by the number of amplifiers that are configured to amplify the difference of an analog signal and a reference voltage. That is, flash ADC 100 can only resolve an analog signal to N or less bits if 2Nxe2x88x921 amplifiers are configured. For example, to achieve 8 bits of resolution 28xe2x88x921=255 amplifiers would be required. Therefore, a flash ADC can quickly become impossible to realize as 2Nxe2x88x921 amplifiers present a large area requirement and consume a very large amount of power. In many environments, it is desirable to achieve higher levels of resolution than those feasible with a single flash ADC. Other types of ADCs, such as the subranging ADC, overcome some of the constraints of flash ADCs.
Subranging ADCs essentially combine the functionality of two or more flash ADCs to increase output resolution. In an N-bit subranging ADC having two flash ADCs, a first flash ADC would convert an analog signal into m coarse bits. Subsequently, through electrical subranging (i.e., refining the value of the reference voltages), a second flash ADC would convert the analog signal into n fine bits, where m+n equals N, the total resolution. Thus, if the individual flash ADCs each had a resolution of 4 bits, a subranging ADC with two of the flash converters could produce a digital representation with 8 bits of resolution. Yet, the subranging amplifier would require only (24xe2x88x921)+(24xe2x88x921)=30 amplifiers.
FIG. 2 illustrates a subranging ADC 200 that utilizes two flash ADCs during the analog-to-digital conversion process. The operation of the subranging ADC 200 will now be described in order to illustrate a conventional subranging ADC technique.
Each amplifier included in coarse flash converter 201 receives the analog input and a coarse reference voltage from reference ladder 202. Reference ladder 202 divides a range of voltages between a minimum and maximum voltage, for example, a range from zero volts to 5 volts, into multiple incrementally increasing coarse reference voltages. For example, using a 0.2 volt increment results in coarse reference values of 0.2 volts, 0.4 volts, 0.6 volts, and so forth. Coarse flash converter 201 uses the analog input and the coarse reference voltages to convert the analog signal into a number of coarse digital values. The coarse digital values are stored in the hold circuit 206 until fine flash converter 204 generates the fine digital bits in a manner that is now to be described.
Reference ladder 202 also divides the range of voltages into multiple incrementally increasing fine reference voltages that more closely approximate the actual value of the analog input signal. This closer approximation is generated using the coarse digital bits as an input and thus the increment for fine reference values is decreased when compared to that used for coarse reference values. However, the fine reference voltages take some amount of time to approach or xe2x80x9csettle toxe2x80x9d their final values since generation of the fine reference voltages is delayed by at least the amount of time taken to generate the coarse digital bits. As such, the analog input must be held at fine flash converter 204 while these fine reference voltages settle. In FIG. 2, analog sample and hold circuit 207 performs this hold function. Typically, sample and hold circuit 207 is a global sample and hold circuit that may be accessed by any of the components included in subranging ADC 200. The circuitry required to implement a sample and hold circuit consumes space, increasing the overall size of subranging ADC 200, and consumes power, increasing the overall power dissipation of subranging ADC 200.
After the fine reference voltages settle, fine reference multiplexer 203 receives the fine reference voltages and the coarse digital values. The coarse digital values are then used to select which of the fine reference voltages best approximate the analog signal at the sampling time. Fine reference multiplexer 203 then outputs those selected fine reference voltages to the fine flash converter 204.
Each amplifier of fine flash converter 204 receives the analog input, which was being held in analog sample and hold circuit 207, and a subranged fine reference voltage. Fine flash converter 204 uses the analog input and the subranged fine reference voltages to convert the analog signal into a number of fine digital values. Encoding logic 205 combines the coarse digital values and fine digital values into a meaningful digital representation of the analog input.
Subranging ADCs are advantageous due to the increased output resolutions that are obtained as compared to using one flash ADC alone for a given number of amplifier sections. However, the combination of multiple flash ADCs also introduces certain drawbacks. As described above, the coarse digital values are generated before the fine reference voltages have time to settle. However, the coarse digital values are required for selecting a subranged portion of the fine reference voltages. Thus, as described, the analog input must be held for some time, for example, in analog sample and hold circuit 207, prior to the calculation of the fine reference voltages. The use of sample and hold circuits increases the manufacturing resources needed to produce ADCs and may introduce errors into the conversion process.
Subranging ADCs are also limited in operational frequency for at least two reasons. One reason is that amplifier arrays require an appropriate amount of time to properly amplify input signals. Conventional timing schemes require two clock partitions (roughly one clock cycle) for proper amplification. Thus, if other components in an ADC perform functions in a single clock partition, the amplification of input signals may be viewed as a bottleneck in the conversion process.
Operational frequency is also limited due to the fine reference voltages requiring an appropriate amount of time to adequately xe2x80x9csettlexe2x80x9d (approach their final potentials) before they are useful to a fine flash converter. A fine flash converter attempting to convert an analog signal into fine digital values before the fine reference voltages have adequately settled increases errors in the conversion process. Conventional timing schemes utilized by subranging converters allow up to two clock partitions for fine reference voltages to settle. Thus, the operational frequency of a subranging converter is sufficiently low such that one full clock cycle is long enough for the fine reference voltages to adequately settle. For example, a subranging converter where 0.001 seconds is an appropriate amount of time for fine reference voltages to adequately settle would be limited to a maximum possible operational frequency of 1 kHz.
Since amplifiers are widely used in flash and subranging ADCs, the performance characteristics of such amplifiers significantly affect the operation of the ADC. There are at least two problems associated with the use of conventional amplifiers in flash and subranging ADCs, and in any ADC that uses amplifiers.
One such problem is cell mismatch, which occurs when each amplifier in the array of amplifiers (such as preamplifiers 102) has different offset voltages. Offset voltage is a voltage difference that must be applied between the input terminals of an amplifier to result in a differential output voltage of zero volts. Even if the design of each amplifier in an amplifier array was identical, inevitable differences in fabrication and manufacturing will typically cause the offset voltage of each operational amplifier to differ somewhat. When an analog input signal and a reference voltage are applied to the input terminals of an array of amplifiers, some amplification error will result due to disparate offset voltages. This amplification error may propagate into other portions of a circuit, such as decision circuits 103, and may affect the accuracy of digital representations of analog signals obtained from analog-to-digital converters.
One technique that reduces the effects of cell mismatch in arrays of amplifiers is xe2x80x9caveraging.xe2x80x9d In circuits that use averaging, resistors or capacitors are connected between corresponding output terminals of adjacent amplifiers. Averaging acts to reduce the effects of cell mismatch by averaging offset voltages over neighboring cells thus increasing accuracy in digital conversion. Implementations of averaging circuits are proposed in U.S. Pat. No. 5,835,048 issued to Klaas Bult for xe2x80x9cAnalog-to-Digital Converter With Improved Cell Mismatch Compensation,xe2x80x9d U.S. Pat. No. 6,014,098 issued to Klaas Bult and Aaron W. Buchwald for xe2x80x9cAnalog-to-Digital Converter,xe2x80x9d and U.S. Pat. No. 6,169,510 issued to Klaas Bult for Analog-to-Digital Converter.xe2x80x9d
FIG. 3 illustrates generally an example of an averaging circuit 300 for an array of differential output amplifiers 302A through 302C. Intermediate capacitors 301 couple each of the output terminals of each amplifier to corresponding output terminals of adjacent amplifiers. The capacitors of intermediate capacitors 301 cause adjacent output terminals, for example those of amplifier 302A and 302B, to be pulled towards the same voltage, thus tending to average any voltage errors.
As previously mentioned, ADCs in the related art typically use voltage-to-voltage or voltage-to-current amplifiers. One typical problem in semiconductor circuits using these types of amplifiers, and thus also common in ADCs employing arrays of these types of amplifiers, is power dissipation. When the number of components in an ADC is increased, the power required to operate ADCs also increases, thereby limiting the scope of applications in which the ADC may operate. Likewise, as power dissipation increases, additional heat is generated, thereby changing the anticipated behavior of the ADC.
One technique that reduces power dissipation in ADCs is interpolation. In circuits utilizing interpolation, the output values of first and second adjacent amplifiers are used to estimate a third xe2x80x9cinterpolatedxe2x80x9d output that is between the first and second output values. Accordingly, the third interpolated output is generated using the first and second amplifiers, but does not use a third amplifier. The interpolated output is then electrically useful for subsequent signal processing, such as an input to a decision circuit, as if there was a third amplifier in between the first and second amplifiers.
Accordingly, the power dissipation is reduced by the amount of power dissipation that would have been present in the third amplifier. In a larger amplifier array, interpolation reduces power dissipation by eliminating the need for a significant number of amplifiers in the array. Moreover, interpolation helps reduce size. Implementations of interpolation circuits are proposed in U.S. Pat. No. 4,912,469 and U.S. Pat. No. 5,051,746 both issued to Robert E. J. van de Grift and Martien van der Veen for xe2x80x9cInterpolation Circuit For Use In A/D Converter.xe2x80x9d
FIG. 4 illustrates generally an example of an interpolation circuit 400 for an array of differential output amplifiers. Interpolated amplifier outputs 404 serve as inputs for decision circuit 403B without being directly output from any amplifier. Interpolated amplifier outputs 404 are coupled by intermediate capacitors 401 to the output terminals of amplifiers 402A and 402C. Due to the capacitive coupling effects of intermediate capacitors 401, the values of interpolated amplifier outputs 404 are pulled to a value between the outputs of amplifier 402A and 402C.
Thus, in the related art, interpolation can be used to reduce the number of voltage-to-voltage or voltage-to-current amplifiers needed for analog-to-digital conversion. However, as shown in FIG. 2, even if the number of amplifiers in an ADC is reduced, a significant number of amplifiers would still be needed to perform analog-to-digital conversion. Further, as the number of amplifiers in an ADC is reduced, the accuracy of the ADC may be affected. Thus, there would need to be some minimum threshold of amplifiers to perform analog-to-digital conversion within a specified level of accuracy. As such, at this minimum threshold of amplifiers, further reduction in power dissipation would need to result from improved performance characteristics (i.e. reduced power dissipation) of the components such as, for example, the amplifiers included in an ADC.
Additionally, conventional averaging and interpolation techniques tend to xe2x80x9cpullxe2x80x9d the outputs of amplifiers on the ends of a sequential amplifier array (the first and last amplifiers) causing distortion. Distortion results at the end amplifiers because these amplifiers are coupled to intermediate capacitors in only one direction. FIG. 5 illustrates a graph 500 that shows the effects of averaging on the outputs of amplifiers at the end of a sequential amplifier array. As shown in FIG. 5, the actual output pulls away from the ideal output at both ends of the conversion range. This pulling away is indicative of distortion. The ""048 patent implements a method using voltage-to-voltage amplifiers to reduce distortion.
For some rudimentary applications, ADC""s using charge-transfer amplifiers have been implemented. For example, U.S. Pat. No. 6,150,851 issued to Ohmi et al. for xe2x80x9cCharge transfer amplifier circuit, voltage comparator, and sense amplifierxe2x80x9d describes an implementation of a 1-bit comparator. The comparator of the ""851 patent includes a charge-transfer amplifier and a latch, the combination of which is used for separating an input voltage into a logical 1 or 0. Subsequently, some increases in resolution have occurred. However, due to the general mode of operation of charge-transfer amplifiers being markedly different from any other class of amplifier, no charge-transfer amplifier based flash ADC with over 4-bits has been implemented. The operation of charge-transfer amplifiers provides significant design related challenges to such an implementation.
Further, even in current implementations, including the 1-bit charge-transfer amplifier based comparator described in the ""851 patent, there is at least one significant disadvantage. Charge-transfer amplifiers typically operate cyclically with each cycle having three phases; (a) a reset phase, (b) a precharge phase, and (c) an amplify phase. At the beginning of the precharge phase charge imbalances occur at the output terminals. Ideally these charge imbalances should be zeroed out before the amplify phase begins. In environments were increased operational frequency is desirable, for example, analog-to-digital converters, there is often insufficient time for these charge imbalances to be zeroed out. Thus, a charge imbalance from a precharge phase may persist into a subsequent amplify phase. Because charge transfer amplifiers are sensitive to charge imbalances, this results in a stored offset voltage. The stored offset voltage can affect the resulting digital output from a latch and increases the chance that incorrect digital logical values are asserted at the outputs of the latch.
It would, therefore, represent an advancement in the art to create charge-transfer amplifier based ADC""s that zero out charge imbalances on latch input terminals. It would represent a further advancement in the art to create ADCs that provide accurate digital output at increased operating frequencies. It would represent yet a further advancement in the art to create ADCs that have reduced power dissipation.
The foregoing problems in the prior state of the art have been successfully overcome by the inventive concepts of the present invention. The present invention includes at least four inventive concepts. A first inventive concept is directed to averaging and interpolation circuits that use transconveyance amplifiers. A second inventive concept is directed to sample and hold circuits where coupling capacitors of a charge transfer amplifier are used to sample and hold an analog signal. A third inventive concept is directed to timing schemes for allowing fine reference voltages to settle. A fourth inventive concept is directed to a comparator where residual charge imbalances at the input terminals of a latch may be significantly reduced.
The first inventive concept is directed to the use of transconveyance amplifiers in averaging and interpolation circuits contained in analog-to-digital converters. Transconveyance amplifiers are voltage-to-charge amplifiers, that is transconveyance amplifiers receive voltage as input and convey a specific amount of charge as output. Due to the electrical characteristics of transconveyance amplifiers, power dissipation in averaging and interpolation circuits using transconveyance amplifiers may be significantly reduced. In some averaging and interpolation circuits the outputs of adjacent transconveyance amplifiers are cross-coupled to reduce distortion.
The second inventive concept is directed to sample and hold circuits where coupling capacitors of a charge transfer amplifier are used to sample and hold an analog signal. Since most charge transfer amplifiers already use coupling capacitors to aid dynamic biasing, no additional components are required to gain sample and hold functionality in an analog-to-digital converter. A novel timing scheme controls when a number of switches open and close so as to hold an input voltage at a terminal of a coupling capacitor of a charge transfer amplifier used in an analog-to-digital converter.
The third inventive concept is directed to timing schemes for allowing fine reference voltages to settle in a subranging analog-to-digital converter. In a subranging analog-to-digital converter, charge transfer amplifiers in a coarse bank of charge transfer amplifiers operate in the amplify phase for one clock partition. Due to the electrical properties of charge transfer amplifiers, charge transfer amplifiers do not suffer substantially from degraded performance through large offset voltages when the length of time for the amplify phase is reduced. Further, the number of clock partitions for allowing fine reference voltages to settle is increased to at least three clock partitions, providing at least a 50% increase in operational frequency over existing timing techniques.
A fourth inventive concept is directed to a comparator where residual charge imbalances at the input terminals of a latch may be significantly reduced. Latch reset switches are controlled by a novel timing scheme to cause charge imbalances to be significantly reduced prior to each amplify phase of a charge transfer amplifier. During the precharge phase of the charge transfer amplifier the precharge voltage is asserted at the input terminals of the latch, while the latch itself remains isolated from the charge transfer amplifier. This allows the latch to recover in a reduced amount of time without any residual charge being transfer to the charge transfer amplifier.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other objects and features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.